Calibration Wafer Standards – 125 mm

Description

125 mm wafers occupy a transitional position in semiconductor manufacturing, larger than early experimental formats but smaller than modern high-volume production sizes. Calibration standards at this dimension support process development, specialized production lines, and mid-generation equipment that was designed around this substrate size. 

Key Applications 

• Calibrate Inspection Tools: 125 mm SSIS tools require calibration against known particle sizes to generate accurate size response curves. This ensures that defect counts and size distributions reported by the tool reflect actual wafer conditions rather than instrument drift or optical artifacts. 

• Tool Qualification & Certification: Qual-Dep™ services use 125 mm standards to establish baseline performance and certify that inspection tools meet operational specifications. This documentation supports both internal quality protocols and external audit requirements. 

• R&D & Development: Dev-Dep™ standards on 125 mm substrates enable sensitivity testing and recipe optimization for new inspection technologies or process modifications before deployment to production. 

• Verify Cleaning Processes: PRE measurement on 125 mm cleaning equipment validates that contamination removal processes achieve target efficiency without excessive chemical use or mechanical damage to the substrate. 

Variation Guide 

• Full Deposit: Particles deposited across the entire 125 mm surface. Used for comprehensive tool qualification to verify scan uniformity and detector response across the full optical sweep.  

• 1-Spot Deposit: Single targeted deposition zone. Appropriate for quick single-size calibration checks, single-point recipe validation, or routine drift monitoring between full qualifications. 

• 2-Spot Deposit: Two localized deposition zones containing different particle sizes. Used to calibrate multi-channel size response and generate sizing curves in a single scan pass without swapping wafers.  

Technical Highlights 

Engineered with PSL spheres, SiO₂, or process particles, each deposit traceable to NIST. These standards supply the reference baseline that enables accurate particle sizing, reliable tool performance documentation, and effective cleaning process optimization for 125 mm semiconductor operations.